`include "s:/define.v"
module cond(
input [3:0] E_op_cnd,
input [2:0] e_cc,
output e_cnd
   );


wire zf = e_cc[2]; 
wire sf = e_cc[1]; 
wire of = e_cc[0]; 


assign e_cnd = 
    (E_op_cnd == `CND_YES) | // all 
    (E_op_cnd == `CND_LE & ((sf^of)|zf)) | // <= 
    (E_op_cnd == `CND_L & (sf^of)) | // < 
    (E_op_cnd == `CND_E & zf) | // == 
    (E_op_cnd == `CND_NE & ~zf) | // != 
    (E_op_cnd == `CND_GE & (~sf^of)) | // >= 
    (E_op_cnd == `CND_G & (~sf^of)&~zf); // >
	 
endmodule
